1. Field of the Invention
The present invention relates to technology for selecting bit lines in a semiconductor storage device, and more particularly to bit line selection technology at the time of successive selections of plural bit lines.
2. Description of Related Art
Conventional semiconductor storage devices split a memory cell array into plural subarrays, and successively selects one bit line from plural bit lines provided in each subarray to read out data. In such a way, they have performed continuous read operation such as burst read access.
As disclosed in Japanese Unexamined Patent Publication No. 2000-132985, an example of a circuit configuration of a nonvolatile semiconductor storage device such as flash memory is shown in FIG. 11. A memory cell array is partitioned into a subarray AA (identified by column address bit A(k+4) of low level) and subarray AB (identified by column address bit A(k+4) of high level), which are identified by column address bit A(k+4) and other address bit(s). Moreover, the individual subarrays AA and AB are split into left areas AA0 and AB0, and right areas AA1 and AB1, and each of the areas has plural nonvolatile transistors disposed at the intersections of plural word lines and plural bit lines. Through nonvolatile transistors selected according to one activated word line WLn of plural word lines, bit lines BL0A to BL15A (subarray AA) and BL0B to BL15B (subarray AB), and ground potential are controlled to connection or non-connection. The existence of a current flowing to a route through the nonvolatile transistors causes data stored in the nonvolatile transistors to be read into the bit lines BL0A to BL15A and BL0B to BL15B. Since the above configuration is the same between the subarrays AA and AB, the subarray AA will be described below.
One bit line is selected from among the bit lines BL0A to BL15A after upper pass gates 210 and 211 and a lower pass gate 220 are controlled by an upper column decoder 11 and a lower column decoder 12, and is connected to a data line DB. In FIG. 11, a selection is made by a four-bit column address bit of column address bits A(k) to A(k+3). The column address bits A(k+1) to A(k+3) are decoded by the upper column decoder 11, and one decode signal YD10 to YD17 is outputted. As a result, proper pass gate transistors within the upper pass gates 210 and 211 are selected. Furthermore, the column address bit A(k) is decoded by the lower column decoder 12, and one of decode signals YD20 and YD21 is outputted. As a result, one of two pass gate transistors within the lower pass gate 220 is selected.
The subarrays AA and AB are identified by column address bit A(k+4) and other address bit(s) not shown. Or, they are identified by being connected to different data buses.
A current-voltage conversion circuit 320 is connected to the data line DB. A current flowing through a route formed by a nonvolatile transistor selected by word line WLn is converted into voltage, and the voltage is compared with a comparison voltage VRF in an amplifier 330 of subsequent stage to perform data amplification.
To continuously perform read operation, a column address is successively incremented. FIG. 12 shows the order of selection bit lines connected to the data line DB as column address is incremented. Each time address is incremented, a lower column address bit A(k) changes. The decode signals YD20 and YD21 are alternately selected. The upper column address bits A(k+1) to A(k+3) are incremented every one cycle of the lower column address bit A(k), and decode signals YD10 to YD17 are selected one after another. As a result, selected bit lines are sequentially selected in the left area AA0 or the right area AA1 while being alternately switched between the left area AA0 and the right area AA1.
At this time, before the changeover of selected bit lines, a reset operation is performed by a reset circuit 310 to discharge a charge between the data line DB and a selected bit line to ground voltage.
In Japanese Unexamined Patent Publication No. H9(1997)-245493, technology is disclosed for disposing a ground shield line between selected bit lines and adjacent non-selected bit lines to prevent interference caused by capacitive coupling between adjacent bit lines.